___ __ | D_|_ | DESIGN AND REUSE |_| &_|_ info@design-reuse.com |_| R | www.design-reuse.com |__ |___| ########################################################################## IP BASED SOC DESIGN'2003 International Workshop & Exhibition on IP based System-on-Chip Design November 13-14, 2003 - Grenoble, France ~~ http://www.us.design-reuse.com/ipbasedsocdesign2003 ~~ ########################################################################## ========================================================================== REGISTRATION DISCOUNT IF YOU REGISTER BEFORE NOVEMBER 3, 2003 http://www.us.design-reuse.com/ipbasedsocdesign2003/registration/ ========================================================================== IP BASED SOC DESIGN'2003 will be the 12th edition of the IFIP workshop on hot topics in the design world, focusing for the past three years on IP based SoC design and qualification. KEYNOTE TALKS ============= Major players will deliver keynote talks on hot topics and you will be delighted to listen to : * "Recent Trends in Multi-Million-Gate Multimedia SOC Designs" by Santanu Dutta, IC Design manager at Philips Semiconductors (U.S.A) * "Design platform for IP based SOC design" by Ted Vucurevich, CTO of Cadence (USA) * "The IP Provider Game: Size and Diversity Do Matter" by Raul Camposano, CTO of Synopsys (USA) * "Dataquest IP business analysis" by Jim Tully from Gartner / Dataquest (UK) HOT PANELS ========== Hot Panels will be part of an attractive program and every participant will be invited to share his views with the audience: * "IP business models: A focus on IP quality and its impact" Organized by P.Dworsky, Synopsys (Director of Marketing, DesignWare IP) (USA) With the participation of : - T. Daniels, LSI Logic (Director, ASIC Technical Marketing) - M. Evans, ARM (Director of IP Licensing) - P. Hirt, ST (IP Procurement Manager) - J. Tully, Gartner/Dataquest (VP and Chief of Research) * "IP qualification : the user camp versus the tool and IP vendor camp" Organized by Philippe Magarshack, ST Microelectronics (France) With the participation of : - Alcatel (France), Philips (The Netherlands), ST Microelectronics (France) in the user camp - ARM (UK), Mentor Graphics (USA), Synopsys (USA), Verisity (USA) in the tool and IP provider camp * "Asic platform: the key for successful IP based SOC design: Core based or interconnect based or technology structured ?" Organized by Tim Daniels, LSI Logic (UK) & Joe Hanson, Altera (USA) With the participation of : - LSI Logic (UK) - Altera (USA) - Sonics (USA) - the Spirit consortium (The Netherlands), etc... * "SystemC in Harmony, not in conflict with RTL" Organized by Guido Arnout, CoWare chairman and OSCI president With the participation of : - IP Vendor: Mark Burton from ARM - EDA Vendor: - Semiconductor Company : Frank Ghenassia from ST - Consumer Company - Training: John Aynsley from Doulos * "Configurable Processors and Reconfigurable Logic: Flexible Architectures for SOCs" Organized by Steve Leibson, Tensilica (USA) With the participation of : - IBM Research Lab (Switzerland), - DAFCA (Design Automation for Flexible Chip Architectures) (USA) - Laboratoire LIRRM (France) - Analyst and editors from Gilder Technology, MicroDesign Resource, Gartner Research (UK) IP/SOC 2003 BEST PRIZES ======================= The contest for delivering the best IP/SOC design 2003 will be organised by Prof. Kunihiro Asada from the Tokyo university. This year 4 candidates preselected by the LSI IP Design Award in Japan will be in competition with 4 additional candidates for winning this prestigious award sponsored by ST Microelectronics * "Variable-integration-time image sensor for wide dynamic range" by Takaya Yasuda from Tokyo University of Science(Japan) Takaya Yasuda, Takahiro Ogi & Takayuki Hamamoto from Tokyo University of Science (Japan) & Kiyoharu Aizawa from University of Tokyo (Japan) * "Real-Time Face Detection Using Six-Segmented Rectangular Filter (SSR Filter) " by O. Sawettanusorn, Y. Senda & H. Yamauchi from Ritsumeikan University (Japan) * "Scalable IP Core of Vector Stream Cipher" by K. Umeno from Communications Research Laboratory and Chaos Ware Inc. (Japan) * "Reconfigurable Processor Device from IPFlex Inc." by T. Sato from IPFlex Inc. (Japan) * "A Low-Power 16-channel AD Converter and Digital Processor ASIC" by R.Esteve-Bosch, B.Mota, L.Musa & A.Jimenez-de-Parga from CERN & D.Subiela, S.Engels & L.Dugoujon from STMicroelectronics * "IP Cores for Accelerating JPEG2000 " by O. Cantineau from Barco Silex (Belgium) * "Creating High performance Resuable 10Gigabit ethernet MACs " by J. Balachandran from IMEC (Belgium), K. Jain & A. Kudale from GDA Technologies (India) & A. Saxena from GDA Technologies (USA) * "IP Core of Statistical Test Suite of FIPS PUB 140-2" by A. Hasegawa & S.-J. Kim from Communications Research Laboratory (Japan) & K. Umeno from Communications Research Laboratory and Chaos Ware Inc. (Japan) WORKING CONFERENCE ================== Among 90 submissions the best technical contributions have been selected to bring together a high level working conference unique on hot topics such as "ASIC Platform","SystemC for IP Modeling" "Impact of Nanometer Technology", "IP/SoC Verification", etc... ########################################################################## SESSION ON IP SOC VERIFICATION ########################################################################## Chairman: D. Wood, Mentor Graphics * "Increased Verification productivity through extensive reuse" by Giles Hall from Verisity Design (UK) * "Functional Verification of a CAN Data Layer Implementation: A Case Study" by A. Souza, J. Sabino & P. Domingues from Motorola (Brazil) * "A Toolkit for Rapid Modeling, Analysis and Verification of SoC Designs" by R. Deaves & A. Jones from SuperH (UK) * "System C Verification, Simulation & Emulation of Secure Digital IP" by Ken Reid from Cadence Design Systems (UK) * "The role of Verification IP in Complex Core Design" by Saverio Fazzari from Cadence Design Systems (USA) ########################################################################## SESSION ON IMPACT OF NANOMETER TECHNOLOGY ########################################################################## Chairman: Huy-Nam Nguyen, Bull * "Selecting the Right Cell Library IP for Nanometer Technology" by Mike Colwell & Gene Sluss from Virage Logic (USA) * "Mixed Signal SoC Applications" by Ron Landry from AMI Semiconductor (USA) * "Maximize Design Flexibility with Fast Turnaround Time while Minimizing Design Costs with Metal Programmable Libraries" by D. Sherlekar, O. Siguenza & H. Yang from Virage Logic (USA) * "?A la Carte? SoCs require innovative IO management" by David Murray from Duolog Technologies (Ireland) * "Improving Design Timing and Simplicity for Lower Cost and High Performance Multistandard Audio Decoder STA012" by M. Bosco from STMicroelectronics (Italy) & S. Bordbar & S. Tiralongo from Synopsys (Italy) ########################################################################## SESSION ON ARCHITECTURAL DESIGN ########################################################################## Chairman: Francois Kleitz, Alcatel * "Hardware/Software Partitioning Methodology for Systems on Chip (SoCs) with RISC Host and Configurable Microprocessors " by S. Takagi, At. Masuda & R. Ohyama from Toshiba (Japan), H. Eichel from Toshiba Electronics Europe (Germany) & N. Matsumoto, Toshiba (Japan) * "Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning" by H. Menager from Philips semiconductors (USA), M. Basel from Mentor Graphics (USA) & R. Kadiyala from Philips semiconductors (USA) * "Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often " by H. Sanghavi, Tensilica (USA) & S. Leibson from Tensilica (USA) * "A Framework for Selection of Cache Configurations for Low Power" by Z. Stamenkovic, F. Vater & Z. Dyka from IHP GmbH (Germany) ########################################################################## OPEN FORUM ON IP BASED SOC DESIGN METHODOLOGY ########################################################################## Chairman: P. Bricaud, Synopsys * "CoreWare? Subsystem based design" by B. Singh from LSI Logic Corporation (USA) * "Chip level IP for Low power Single chip Wireless Transceivers" by C. Faulkner from Jennic (UK) * "Methodology for flow integrations in a SOC design " by P. Guruswamy from Wipro (India) & H. Kwan from Texas Instruments (USA) * "System Design Methodologies for System-on-Chip and Embedded Systems" by E. Blokken , J. Vounckx, J. Bormans, S. Vernalde & P. Wambacq from IMEC * "An analysis and implementation of high fairness arbitration mechanism by using level-table and static priority orders in shared bus architecture " by J. Suh & H.-J. Yoo from Korea Advanced Institute of Science and Technolgy * "Reliability-based Characterization of Semiconductor IP in SoC Design" by You-Pang Wei & Bill Wasserman from Legend Design Technology, Inc. (USA) ########################################################################## SESSION ON REUSE PRACTICE ########################################################################## Chairman: Prof. Mori, IPTC (Japan) * "Lessons learnt in IP Reuse " by C.Gendarme, F.Kleitz & I.Hrynchyshyn from Alcatel (France, Belgium), G .Saucier & K.Skiba from Design and Reuse (France), K.Benseffaj, A.Hanczakowski & M.Vandendriessche from STMicroelectronics (France) * "VSI Alliance Quality IP Metric " by K. Werner from Mentor Graphics (USA) * "IP Core-centric ommunications protocol" by F. Seigneret from Texas Instruments (France) & OCP-IP Specification Working Group ########################################################################## SESSION ON ASIC PLATFORM ########################################################################## Chairman: T. Daniels, LSI Logic (UK) * "Store and Forward Fat-Tree Architecture for on-Chip Networks" by Filippo Mondinelli from University of Brescia (Italy) * "SBAG : The on-chip STBus traffic analyzer" by Bernard Ramanadin from STMicroelectronics (France) * "CCP: Customizable Control Processor" by Juergen Hilsberg, IBM (Switzerland) * "Spirit Compliant Platform Design using an IP Repository" by Mark Peryer from Mentor Graphics (UK) * "An ASIC Platform Manager" by G.Saucier, K.Skiba & P.Coeurdevey from Design And Reuse (France) & H.N. Nguyen from METASymbiose S.A. (France) * "Structured ASIC Based SoC Design" by Rick Mosher from AMI Semiconductor (USA) ########################################################################## SESSION ON SYSTEMC FOR IP MODELLING ########################################################################## Chairman: J. Hasse, EDACentrum * "A Fast SystemC Simulation Methodology for Multi-level IP/SoC Design" by Samy Meftali from LIFL (France) * "IP-Based SOC Design in a in-house C-based design methodology" by Marcello Lajolo from NEC (USA) * "Architectural Exploration of Low-Power CORDIC Engine using Transaction-Level Models " by W. Cheng, P. Wu, L. Mastroleon from Stanford University (USA) and M. Hakansson from CoWare (USA) ########################################################################## OPEN FORUM ON SYSTEMC FOR IP MODELLING ########################################################################## Chairman: G. Arnoux, Coware * "SoC Integration of Programmable Cores " by A. Wieferink & T. Kogel from RWTH Aachen (Germany) & A. Hoffmann, O. Zerres & A. Nohl from CoWare Inc. (USA) * "Architectural Analysis For A Multiprocessor SoC Using SystemC" by Mallik Moturi from Hughes Network Systems (USA) * "Transactional level as the new design and verification abstraction above RTL" by Bart Vanthournout from CoWare (Belgium) ########################################################################## SESSION ON RECONFIGURABLE IP AND SOC ########################################################################## Chairman: L. Torres, LIRRM * "The CREC Reconfigurable Computer" by O. Cret from Technical University of Cluj-Napoca (Romania) * "3+ Ways to Design Reconfigurable Algorithm Accelerator IP Block " by Tapio Ristim„ki from Tampere University Of Technology / Institute of Digital and Computer Systems (Finland) * "FPGA Coprocessors: Hardware IP for Software Engineers" by Robert Cottrel from Altera (UK) ########################################################################## SESSION ON IP BASED SOC DESIGN ########################################################################## Chairman: A. Bruening, sci-worx (Germany) * "An IP Based Design Flow with ASIPs for the Design and Implementation of Digital Filters" by Sven Simon from Hochschule Bremen (Germany) * "Low-power Motion Estimation IP for MPEG-4" by Hongkyu Choi from Yonsei Univ. EE. (Republic of Korea) * Application of SoC in 4G Mobile Telephony Baseband Chip" by Rohan Sarker from Reliance Industries Limited (India) * "Design of a SoC for Low cost IC Testing" by Liakot Ali from University Putra Malaysia (Malaysia) * "Concepts and implementation of the Philips Network-on-Chip " by John Dielissen from Philips ########################################################################## OPEN FORUM ########################################################################## Chairman: P. Blouet, STMicroelectronics * "IP Based System Design for Aerospace and Military - The Time is now" by P. Southard from PDS Consulting, LLC (USA) & T. Ivey from MTI (USA) * "Performance: The Future of Embedded Processing " by Tom Petersen from MIPS Technologies, Inc. (USA) * "An IP Based SoC Design - Reduces System Design Time" by Kiran Patel from Silicon Interfaces Pvt Ltd (India) * "System for Active Design Knowledge Preservation and Reuse" by Chia-Huei Lee from Springsoft / Novas (Taiwan) * "Sophocles: Cyber-Enterprise for System-On-Chip Distributed Simulation -- Model Unification" by Pierre Boulet from LIFL (France) * "Muti Chip, Multi Environment Simulation. Bringing Software closer to Hardware and saving $$" by Swaminathan Venkatesan from Wipro Technologies (India) * "Increased Verification productivity through extensive reuse" by Giles Hall from Verisity Design (UK) * "Dead Horse or Sleeping Beauty - Will Embedded FPGAs Have a Role in Future SoC-Designs?" by Thomas Niedermeier from Infineon Technologies (Germany) * "Benefits of Reconfigurable IP in the Back-end SoC Development Process" by Kenn Lamb from Elixent Ltd (UK) * "New architecture for Configurable blocks using Differential" by Manjunath R & Gurumurthy from UVCE (India) To read the program, go to : http://www.us.design-reuse.com/ipbasedsocdesign2003/program/ EXHIBITION ========== In addition the "IP based SOC Design Workshop" has an exhibition attached, giving you the opportunity to see the reality of a SOC connected world. The joint exciting dedicated exhibition will allow you to meet the most advanced suppliers and take the chance to see the last products of the best vendors including Artisan Components, Barco Silex, Coware, Design And Reuse, Jennic Ltd., Legend Design Technology, Mentor Graphics, Novas Software, OCPIP, PLD Applications, Prosilog, Silicon and Software Systems, Soisic, Synchronicity, Synopsys, Target Compiler, VCX Software Ltd., Verisity, Virage Logic You can still book your space. http://www.us.design-reuse.com/ipbasedsocdesign2003/exhibition/ SEMINAR ======= A seminar takes place November 12th evening and has as objectives to report to the IP/SOC community and especially to D&R partners the role and achievement of D&R. Entrance is free but registration is required : http://www.us.design-reuse.com/ipbasedsocdesign2003/seminar/ LOCATION ========= Espace Congres du World Trade Center 5 place Robert Schuman 38 000 Grenoble FRANCE REGISTRATION ============ Registration Discount if your register before November 3, 2003 http://www.us.design-reuse.com/ipbasedsocdesign2003/registration/ LAST MINUTE =========== The foils of the presentations of the previous edition are available online, see : http://www.us.design-reuse.com/ipbasedsocdesign/ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ AROUND WWW.DESIGN-REUSE.COM ---------------------------- * SPONSOR MESSAGE : True Circuits, Inc. offers a family of standardized clock generator, deskew, low-bandwidth and spread-spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC designers. These high-quality, low-jitter, silicon-proven hard macros are available for immediate delivery in a range of frequencies, multiplication factors and functions in TSMC, UMC and Chartered processes from 0.25 to 0.09 micron. Call (650) 691-2500 or visit http://www.truecircuits.com/dr3 * SOC NEWS ALERTS Receive free news updates related to the SoC field on your desktop on a regular basis, go to : http://www.us.design-reuse.com/users/change_settings.php * MISSED IP BASED DESIGN 2002 ???? The presentations are available online, go to : http://www.us.design-reuse.com/ipbasedsocdesign ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ CHANGE OF ADDRESS/UNSUBSCRIBE ----------------------------- You are subscribed as dolinsky@gsu.by * If you wish to unsubscribe or if you wish to receive this letter in "HTML" format, you can do it there: http://www.us.design-reuse.com/users/newsletter.php?u=32546&e=dolinsky@gsu.by * If you need to change the e-mail address at which you receive this newsletter, you can do it there http://www.us.design-reuse.com/users/change_settings.php ============================================================= DESIGN AND REUSE "The Catalyst of Collaborative SoC Design through IP Exchange" www.design-reuse.com ============================================================= Corporate Headquarters: World Trade Center 5 place Robert Schuman 38025 Grenoble Cedex FRANCE Tel: +33 476 70 64 87 Fax: +33 476 70 64 53 info@design-reuse.com US office: 5600 Mowry School Road Suite 180 Newark, CA 94560 USA Tel: +1 510 656 1445 Fax: +1 510 656 0995 info@design-reuse.com